Responsibilities Dealing with block level DFT design which includes Scan/MBIST/IP test in a large-scale chip. Design synthesis & assist Physical Design team for DFT timing closure. Responsible for DFT verification and simulation. Support test team for test program debugging. Qualifications Bachelor degree and above in Electrical & Electronic Engineering, Computer Science or equivalent. Knowledge of DFT principles. Experience with Scan/ijtag/MBIST circuit structures and principles. Experience with VCS or Verdi. Knowledge of STA. Knowledge of ATE is a plus. Able to improve work efficiency by automation using scripting languages, such as Python and Perl is a plus. Seniority level
Mid-Senior level Employment type
Full-time Job function
Manufacturing and Information Technology Industries
Blockchain Services
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